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Zhejiang University Chinese

ACADEMICS

Modern VLSI Process Technology

Editor: Date:2019-11-14 Hits:29

Modern VLSI Process Technology

ModuleSyllabus

 

Lecture 1 (1 hour) Introduction of Modern VLSI Process Technology

Lecture 2 (1 hour) Crystal Growth and Wafer Preparation

Lecture 3 (2 hours) Thin Films and Epitaxy

Lecture 4 (6 hours) Dielectric Film and Polysilicon Deposition

Lecture 5 (2 hours) Lithography

Lecture 6 (4 hours) Advanced Lithography

Lecture 7(6 hours) Wet and Dry Etching Processes

Lecture 8(2 hours) Ion Implantation and Diffusion

Lecture 9(4 hours) Interconnect Technology and Reliability

Lecture 10 (3 hours) Process Integration and MOSFET Basics

Lecture 11(1 hour) Characterization Techniques for VLSI Fabrication

Course description:This module aims to introduce the fundamentals of integrated-circuit (IC) fabrication technology to students, so as to provide the students a basic understanding of IC processes and the effect of processing choices on device performance. Students will learn and familiarize the IC fabrication process with the aid of lectures and necessary hands-on practice.  The lecture part will cover the contemporarily used processing techniques and design methodologies of microfabrication. Process modules including epitaxy, thermal oxidation, thin film deposition, lithography, etching, diffusion, ion implantation, and metallization will be introduced. The laboratory part of the course will provide students opportunities to have hands-on experience to simulation tools and to fabricate and characterize some basic MOSFET transistors.

Biography of lecturers:

Yi Zhao (Prof.) received the Ph.D degree fromthe University of Tokyo, Tokyo, Japan, in 2007.His Ph.D. study was focused on lanthanum-basedhigh-permittivity (k) gate dielectrics.From July 2003 to September 2004, he was a Research and DevelopmentEngineer with Shanghai Hua Hong NEC (HH-NEC), Shanghai, China,where he was engaged in the research and development of 0.25-, 0.18-, and0.13-μm CMOS processes, specially in the wafer-level reliability evaluationand test structure design. After finishing his Ph.D. study, he was a ResearchFellow for half a year with the Quantum-Phase Electronics Center, Universityof Tokyo. From April 2008 to March 2010, he was a JSPS Postdoctoral Fellowwith the Department of Electrical Engineering and Information Systems,School of Engineering, University of Tokyo, where he was engaged in theresearch on the physics of strained-Si MOS devices. Since April 2010, hehas been a Project Assistant Professor with the Institute of Industrial Science,University of Tokyo. His recent research interests include advanced CMOSdevices using new channel materials and the variation in 40- and 65-nm CMOSdevices for SRAM and logic applications. From 2011 to 2012, he worked at Globalfoundries/IBM Allliance as a R&D engineer, focusing on 28 nm and 14 nm technology nodes.Now, he is the full professor of School of Microelectronics, Zhejiang University.Dr. Zhao is a Senior Member of the IEEE Electron Devices Society.

Ran Cheng (Assis. Prof.) received the B.Eng. and Ph.D degrees in Electrical Engineering from National University of Singapore, Singapore in 2009 and 2014, respectively.  Her Ph.D study focuses on the performance engineering of advanced transistors with novel materials and structures.  She fabricated high performance strained Ge nanowire FET with only 3.5 nm-in-diameter. From late 2014 to 2017, she joined School of Microelectronics, Zhejiang University as a postdoctoral researcher, and in mid-2017, she became an assistant professor in Zhejiang University.  Her research interests include strain engineering, device modelling and simulation, and ultrafast characterization technology for advanced logic transistors etc.She has author and co-authored over 40 papers in top conferences and journals including IEDM, VLSI, TED, EDL etc.  Dr. Cheng is a member of the IEEE Electron Devices Society.


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